The lower layer of communication networks like the connectivity layer in a core network of a cellular environment could be seen as a layer of distributed resources for managing data flows. Some of the main nodes comprised in such networks are switches routing and directing data from input to output lines. Reliable internal synchronisation in these switches is crucial i.a. for keeping bit slips through the switches as low as possible.
The switches are normally equipped with internal Time Division Multiplex buses leading frames consisting of time slots of data from the receiving to the transmitting side of the switch in a predefined way. For a regular transmission of the frames, they are synchronised with a master timer initiating transmission of each frame.
The H.110 standard specifies that inside a node, e.g. a switch, there will be two potential providers of the master timing, primary master and secondary master. The purpose of having two master timers is that if the primary master fails, the secondary master will take over the timing in the node. Reasons for this may be line failure in some of the input lines, signal of poor quality, power outage, etc.
The clock sources for the primary and secondary master are reference signals, netref#1, and netref#2. Any of the serial input ports in a node can be the source for netref#1 and netref#2. These clocks are synchronised to the specific timing in the network.
However, the problem area is not specially related to the H.110 solution, but acts as an example. To illustrate the problem this document issues, an additional example system is taken into consideration, namely the Plesichronous Digital Hierarchy (PDH). PDH is a transmission protocol normally applied for data transmission at data rate magnitudes of 64 kbit/s to 139,264 Mbit/s.
FIG. 1 shows a simplified block diagram and timing diagram of the synchronisation mechanism in a PDH system. One of two (or more) references that are usually extracted from serial data links is used as the timing reference for a master frame synchronisation signal. The references (REF1 and REF2) and the frame synchronisation signal (FRAME_SYNC) are usually 8 kHz signals (125 us period) indicating one TDM frame.
REF1 and REF2 may have an arbitrary phase relation. A PLL is mainly used for jitter attenuation and to smooth out phase variations at switch-over from one reference to another. An external select signal (SEL) selects whether REF1 or REF2 shall be chosen as timing reference. At switch-over from one reference to another (i.e. when the chosen reference disappears or if the quality of the reference is poor), the phase difference between the references will lead to a phase jump on the input of the PLL. This will gradually lead to a phase change on the frame synchronisation signal. The phase change may be up to one period of the reference signals (worst case). The two worst-case phase jump conditions are illustrated in FIG. 2 and FIG. 3.
A FIFO is normally placed ahead of the TDM bus for reducing the effect of data rate variations and small phase irregularities. However, such FIFOs are not dimensioned to absorb large phase jumps, as the use of deep FIFOs lead to longer timing delays and more logic. Thus, the phase jump in the frame synchronisation signal as described above, may result in an overflow in the FIFO, which in turn would lead to bit slips and bit errors, and resynchronisation and retransmission of data at switch-over from one timing reference to another may be necessary.
WO 98/25367 and WO 98/25368 disclose variants of a method of generating a system clock signal periodically locked to a selected one of a plurality of phase-locked loops, each of which emitting a clock signal in phase-locked relationship with an external reference signal. A digital error signal is transferred from the selected phase-locked loop to a central numerically controlled oscillator, and the system clock is locked to the output signal from the central numerically controlled oscillator.
U.S. Pat. No. 5,909,149 discloses a multi-band locked loop employing multiple switchable voltage controlled oscillators. A single PLL is provided having a different voltage controlled oscillator for each desired frequency band. The transfer function of the phase detector in the phase-locked loop is switched responsive to the particular band selected for maintaining the loop natural frequency at the same point regardless of other changes in the loop transfer function, such as changes in the frequency slope of the voltage controlled oscillators and changes in the division ratio of the loop divider circuit.
One of the drawbacks of WO 98/25367 and WO 98/25368 is that much logic is necessary since several phase detectors and numerically controlled oscillators are required. This contributes to a very complicated solution. In addition, a digital error signal must be integrated over a period of time.
U.S. Pat. No. 5,909,149 is truly related to problems with switching between two frequency references, but it only concerns switching problems that occur when switching from one frequency band to another, and not phase jumps between two references with the same frequency. Thus, the publication does not solve this problem since it is not attenuating phase jumps when switching between the frequency references.